Semiconductor memory device
US10074667B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Aug 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.