Patent · US Active

Device with transistors distributed over several superimposed levels integrating a resistive memory

US10074802B2 · kind B2 · utility

0Cited by

1References

11Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Claire Fenouillet-Beranger · Grenoble, FR
Elisa VIANELLO · Grenoble, FR

Key dates

Filing date	Nov 30, 2016
Grant date	Sep 11, 2018
Priority date	—
Expiry date	Nov 30, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10N70/8833

Abstract

Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.