Wafer level electrical test for optical proximity correction and/or etch bias
US10078107B2 · kind B2 · utility
0Cited by
3References
11Claims
0Family size
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Key dates
| Filing date | Oct 27, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.