Semiconductor chip package comprising laterally extending connectors
US10079195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/003
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.