Patent · US Active

Translating virtual memory addresses to physical addresses

US10083124B1 · kind B1 · utility

1Cited by
4References
20Claims
0Family size

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Key dates

Filing dateMar 22, 2017
Grant dateSep 25, 2018
Priority date
Expiry dateMar 22, 2037

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2212/681
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A translation engine for a processor system to translate virtual memory addresses to physical addresses of a main memory of a computer system is provided, where a sequence of accesses to multiple address translation tables is performed to support a computer system virtualization level. The translation engine includes: a first pipeline having at least, a first pipeline stage to receive a value for an original address or an address translation table entry requested in a previous pass through the first pipeline; a second pipeline stage using the value as an operand in a translation operation eventually yielding the address translation result or yielding a table index to an entry in a next address translation table; and a third pipeline stage issuing a read request for the entry in the next address translation table.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.