Gate cut with integrated etch stop layer
US10083961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2016 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Dec 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.