Marc A. Bergendahl
115Patents
12h-index
76Co-inventors
89Inventor score
Filing activity: Mar 28, 2002 → Aug 7, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9666528B1 | BEOL vertical fuse formed over air gap | Electricity | 403 | Active |
| US9608065B1 | Air gap spacer for metal gates | Electricity | 89 | Active |
| US9620590B1 | Nanosheet channel-to-source and drain isolation | Electricity | 86 | Active |
| US9799765B1 | Formation of a bottom source-drain for vertical field-effect transistors | Electricity | 25 | Active |
| US8785284B1 | FinFETs and fin isolation structures | Electricity | 24 | Active |
| US9905643B1 | Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors | Electricity | 22 | Active |
| US8906807B2 | Single fin cut employing angled processing methods | Electricity | 20 | Active |
| US9177820B2 | Sub-lithographic semiconductor structures with non-constant pitch | Electricity | 19 | Active |
| US8492274B2 | Metal alloy cap integration | Electricity | 18 | Active |
| US8896067B2 | Method of forming finFET of variable channel width | Electricity | 16 | Active |
| US8941156B2 | Self-aligned dielectric isolation for FinFET devices | Electricity | 13 | Active |
| US9450095B1 | Single spacer for complementary metal oxide semiconductor process flow | Electricity | 13 | Active |
| US8003512B2 | Structure of UBM and solder bumps and methods of fabrication | Electricity | 12 | Active |
| US9449871B1 | Hybrid airgap structure with oxide liner | Electricity | 12 | Active |
| US10083961B2 | Gate cut with integrated etch stop layer | Electricity | 11 | Active |
| US9263290B2 | Sub-lithographic semiconductor structures with non-constant pitch | Electricity | 8 | Active |
| US9780027B2 | Hybrid airgap structure with oxide liner | Electricity | 8 | Active |
| US10014391B2 | Vertical transport field effect transistor with precise gate length definition | Electricity | 8 | Active |
| US10074730B2 | Forming stacked nanowire semiconductor device | Electricity | 8 | Active |
| US8629511B2 | Mask free protection of work function material portions in wide replacement gate electrodes | Electricity | 7 | Active |
| US10211055B2 | Fin patterns with varying spacing without fin cut | Electricity | 7 | Active |
| US9728622B1 | Dummy gate formation using spacer pull down hardmask | Electricity | 7 | Active |
| US8716127B2 | Metal alloy cap integration | Electricity | 5 | Active |
| US10381437B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
| US10043801B2 | Air gap spacer for metal gates | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.