Semiconductor device including a superlattice and replacement metal gate structure and related methods
US10084045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Jun 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
Abstract
A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.