Inventor · Sakaki, JP

Hideki Takeuchi

105Patents
29h-index
97Co-inventors
93Inventor score

Filing activity: Oct 30, 1975 → Jul 2, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9275996B2 Vertical semiconductor devices including superlattice punch through stop layer and related methods Electricity 103 Active
US9406753B2 Semiconductor devices including superlattice depletion layer stack and related methods Electricity 98 Active
US9899479B2 Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods Electricity 83 Active
US10084045B2 Semiconductor device including a superlattice and replacement metal gate structure and related methods Electricity 68 Active
US9941359B2 Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods Electricity 65 Active
US9972685B2 Vertical semiconductor devices including superlattice punch through stop layer and related methods Electricity 59 Active
US7217243B2 Ultrasound diagnosis apparatus Human Necessities 59 Expired
US10170603B2 Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers Electricity 57 Active
US10170604B2 Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers Electricity 56 Active
US10304881B1 CMOS image sensor with buried superlattice layer to reduce crosstalk Electricity 48 Active
US10249745B2 Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice Electricity 48 Active
US10593761B1 Method for making a semiconductor device having reduced contact resistance Electricity 44 Active
US10367028B2 CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice Electricity 43 Active
US10580866B1 Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance Electricity 42 Active
US10608043B2 Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice Electricity 41 Active
US10615209B2 CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice Electricity 40 Active
US10529757B2 CMOS image sensor including pixels with read circuitry having a superlattice Electricity 40 Active
US10396223B2 Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk Electricity 40 Active
US10381242B2 Method for making a semiconductor device including a superlattice as a gettering layer Electricity 40 Active
US10529768B2 Method for making CMOS image sensor including pixels with read circuitry having a superlattice Electricity 40 Active
US10453945B2 Semiconductor device including resonant tunneling diode structure having a superlattice Electricity 40 Active
US10355151B2 CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk Electricity 40 Active
US10580867B1 FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance Electricity 40 Active
US10461118B2 Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk Electricity 40 Active
US5693223A Column and column device for low pressure-high speed liquid chromatography and a method for using said column device Physics 40 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.