Patent · US Active

Cache allocation with code and data prioritization

US10089229B2 · kind B2 · utility

3Cited by

0References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Andrew J. Herdrich · Hillsboro, US
Edwin Verplanke · Chandler, US
Ravishankar Iyer · Portland, US
Christopher C. Gianos · Sterling, US
Jeffrey D. Chamberlain · Tracy, US
Ronak Singhal · Portland, US
Julius Mandelblat · Haifa, IL
Bret L. Toll · Hillsboro, US

Key dates

Filing date	Jan 9, 2017
Grant date	Oct 2, 2018
Priority date	—
Expiry date	Jan 9, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/604
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.