Vertical FINFET structure and methods of forming same
US10090204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure is directed to an integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a set of fins within an ILD layer on a substrate; a first gate dielectric over the substrate and extending along opposing sidewalls of each fin in the set of fins, a metal stack adjacent to the first gate dielectric and on the opposing sidewalls of each fin, the metal stack having a first portion over the substrate and a second portion contacting the first gate dielectric and extending along the opposing sidewalls of each fin, wherein at least the first portion of the metal stack and a portion of the first gate dielectric above the substrate is replaced by another dielectric material; a set of epitaxial regions within the ILD layer; and a conductor within the ILD layer and extending over each epitaxial region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.