3D stacked multilayer semiconductor memory using doped select transistor channel

US10090316B2 · kind B2 · utility

Assignee

• ASM IP Holding B.V. · NL

Inventor

• Fumio Ootsuka · Tokorozawa, JP

Key dates

• Filing date: Sep 1, 2016
• Grant date: Oct 2, 2018
• Expiry date: Dec 29, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50

Abstract

In 3D stacked multilayer semiconductor memories including NAND and NOR flash memories, a lightly boron-doped layer is formed on top of a heavily boron-doped layer to form a select transistor, wherein the former serves as a channel of the select transistor and the latter serves as an isolation region which isolates the select transistor from a memory transistor.