Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure
US10090318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Aug 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the verti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.