Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates

US10090402B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Chanro Park · Clifton Park, US
• Chang Ho Maeng · Ballston Spa, US
• Pei Liu · Clifton Park, US
• Junsic Hong · Malta, US
• Laertis Economikos · Hopewell Junction, US
• Ruilong Xie · Niskayuna, US

Key dates

• Filing date: Jul 25, 2017
• Grant date: Oct 2, 2018
• Expiry date: Jul 25, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/011

Abstract

The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.