Memory system including multi-plane flash memory and controller
US10096366B2 · kind B2 · utility
6Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2016 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Apr 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.