Method for fabricating electronic package
US10096541B2 · kind B2 · utility
0Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2017 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Aug 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.