Trapping gate forming process and flash cell
US10096611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Jul 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.