Gate metal patterning for tight pitch applications
US10103065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Apr 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.