Semiconductor devices and processing methods
US10103123B2 · kind B2 · utility
2Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.