Method and design of low sheet resistance MEOL resistors
US10103139B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Jul 7, 2015 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jul 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes: a semiconductor substrate; a shallow trench isolation (STI) region in the semiconductor substrate; one or more active devices formed on the semiconductor substrate; and a resistor array having a plurality of resistors disposed above the STI region; wherein the resistor array comprises a portion of one or more interconnect contact layers that are for interconnection to the one or more active devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.