Semiconductor device having insulating layer higher than a top surface of the substrate, and method for reducing the difficulty of filling an insulating layer in a recess
US10103150B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 3, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.