Ying-Chiao Wang
41Patents
5h-index
68Co-inventors
72Inventor score
Filing activity: May 18, 1998 → Apr 30, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6075203A | Photovoltaic cells | Emerging Cross-Sectional Technologies | 49 | Expired |
| US10074656B1 | Semiconductor memory device and manufacturing method thereof | Electricity | 12 | Active |
| US9929162B1 | Semiconductor device and method for forming the same | Electricity | 7 | Active |
| US10068907B1 | Dynamic random access memory | Electricity | 6 | Active |
| US9960167B1 | Method for forming semiconductor device | Electricity | 6 | Active |
| US10181473B2 | Semiconductor device | Electricity | 4 | Active |
| US6720202B2 | Photovoltaic cells | Emerging Cross-Sectional Technologies | 4 | Expired |
| US10361209B2 | Semiconductor memory device | Electricity | 3 | Active |
| US10854676B2 | Semiconductor device having capped air caps between buried bit lines and buried gate | Electricity | 3 | Active |
| US10169521B2 | Method for forming contact plug layout | Electricity | 2 | Active |
| US11049863B2 | Semiconductor structure with capacitor landing pad and method of making the same | Electricity | 2 | Active |
| US9773887B2 | Semiconductor device and method for fabricating the same | Electricity | 2 | Active |
| US11508614B2 | Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate | Electricity | 2 | Active |
| US9679901B1 | Semiconductor device and manufacturing method thereof | Electricity | 2 | Active |
| US10672864B2 | Manufacturing method of semiconductor memory device | Electricity | 1 | Active |
| US10276650B2 | Semiconductor memory device and manufacturing method thereof | Electricity | 1 | Active |
| US9659873B2 | Semiconductor structure with aligning mark and method of forming the same | Electricity | 1 | Active |
| US10170481B2 | Semiconductor memory device and method of forming the same | Electricity | 1 | Active |
| US9960123B2 | Method of forming semiconductor structure with aligning mark in dicing region | Electricity | 1 | Active |
| US10475648B1 | Method for patterning a semiconductor structure | Electricity | 0 | Active |
| US10103150B1 | Semiconductor device having insulating layer higher than a top surface of the substrate, and method for reducing the difficulty of filling an insulating layer in a recess | Electricity | 0 | Active |
| US10249510B1 | Etching method | Electricity | 0 | Active |
| US10204914B2 | Method for fabricating semiconductor device | Electricity | 0 | Active |
| US10490557B2 | Semiconductor structure with contact plug and method of fabricating the same | Electricity | 0 | Active |
| US10553591B2 | Semiconductor memory device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.