Method for manufacturing a high-voltage FinFET device having LDMOS structure
US10103248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Mar 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.