Structure and method for vertical tunneling field effect transistor with leveled source and drain
US10103253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2015 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jun 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.