Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic
US10114920B1 · kind B1 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Jun 29, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Dec 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.