Inventor · Noida, IN

Prashant Sethia

11Patents

6h-index

25Co-inventors

62Inventor score

Filing activity: Mar 15, 2013 → Aug 24, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8788995B1	System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design	Physics	43	Active
US8863052B1	System and method for generating and using a structurally aware timing model for representative operation of a circuit design	Physics	36	Active
US9875333B1	Comprehensive path based analysis process	Physics	36	Active
US10776547B1	Infinite-depth path-based analysis of operational timing for circuit design	Physics	14	Active
US9589096B1	Method and apparatus for integrating spice-based timing using sign-off path-based analysis	Physics	10	Active
US9633159B1	Method and system for performing distributed timing signoff and optimization	Physics	6	Active
US10289774B1	Systems and methods for reuse of delay calculation in static timing analysis	Physics	5	Active
US9405882B1	High performance static timing analysis system and method for input/output interfaces	Physics	5	Active
US9529962B1	System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design	Physics	4	Active
US10114920B1	Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic	Physics	3	Active
US12423504B1	Adaptive path based analysis process	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.