Semiconductor memory device including a control circuit and at least two memory cell arrays
US10120584B2 · kind B2 · utility
11Cited by
8References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 16, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Jun 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.