Bad column management with data shuffle in pipeline
US10120816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Apr 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.