Architecture material and process to improve thermal performance of the embedded die package
US10121722B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Sep 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.