Floating body memory cell having gates favoring different conductivity type regions
US10121792B2 · kind B2 · utility
8Cited by
6References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Oct 9, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.