Method of manufacturing semiconductor memory device
US10121869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Dec 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.