Logical interleaver
US10122384B2 · kind B2 · utility
0Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Jun 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.