Assessment of HCI in logic circuits based on AC stress in discrete FETs
US10126354B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jun 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
CMOS switching devices are connected to testing equipment that applies AC to stress the CMOS switching devices. The testing equipment varies rise and fall times of drain and gate voltages, and varies offsets of the drain and gate voltages of the CMOS switching devices. The amount of hot carrier injection (HCI) within the CMOS switching devices is measured when the rise and fall times of the drain and gate voltages cross over, to establish AC HCI contribution to device degradation of the CMOS switching devices. Further, these methods can correlate the AC HCI contribution of the CMOS switching devices to CMOS logic devices based on ring oscillator (RO) degradation of ROs similarly tested or simulated, to produce AC HCI contribution for the CMOS logic devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.