Bandwidth increase in branch prediction unit and level 1 instruction cache
US10127044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Sep 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.