Inventor · Santa Clara, CA, US

Marius Evers

31Patents
4h-index
55Co-inventors
66Inventor score

Filing activity: Oct 4, 2004 → Dec 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7818592B2 Token based power control mechanism Emerging Cross-Sectional Technologies 19 Active
US10929141B1 Selective use of taint protection during speculative execution Physics 7 Active
US11868777B2 Processor-guided execution of offloaded instructions using fixed function operations Emerging Cross-Sectional Technologies 6 Active
US7188325B1 Method for selecting transistor threshold voltages in an integrated circuit Physics 6 Expired
US9058277B2 Dynamic evaluation and reconfiguration of a data prefetcher Emerging Cross-Sectional Technologies 3 Active
US7702888B2 Branch predictor directed prefetch Physics 2 Active
US11048506B2 Tracking stores and loads by bypassing load store units Physics 2 Active
US11334384B2 Scheduler queue assignment burst mode Physics 1 Active
US12153926B2 Processor-guided execution of offloaded instructions using fixed function operations Emerging Cross-Sectional Technologies 1 Active
US10915322B2 Using loop exit prediction to accelerate or suppress loop mode of a processor Emerging Cross-Sectional Technologies 1 Active
US11256505B2 Using loop exit prediction to accelerate or suppress loop mode of a processor Emerging Cross-Sectional Technologies 1 Active
US10949201B2 Processor with accelerated lock instruction operation Physics 1 Active
US8086825B2 Processing pipeline having stage-specific thread selection and method thereof Physics 1 Active
US10956157B1 Taint protection during speculative execution Physics 1 Active
US11416256B2 Selectively performing ahead branch prediction based on types of branch instructions Physics 1 Active
US11620224B2 Instruction cache prefetch throttle Physics 1 Active
US10127044B2 Bandwidth increase in branch prediction unit and level 1 instruction cache Physics 1 Active
US12204908B2 Storing incidental branch predictions to reduce latency of misprediction recovery Physics 0 Active
US9916243B2 Method and apparatus for performing a bus lock and translation lookaside buffer invalidation Physics 0 Active
US11055098B2 Branch target buffer with early return prediction Physics 0 Active
US9697146B2 Resource management for northbridge using tokens Physics 0 Active
US10956332B2 Retaining cache entries of a processor core during a powered-down state Emerging Cross-Sectional Technologies 0 Active
US10671535B2 Stride prefetching across memory pages Physics 0 Active
US10732979B2 Selectively performing ahead branch prediction based on types of branch instructions Physics 0 Active
US10896044B2 Low latency synchronization for operation cache and instruction cache fetching and decoding instructions Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.