Reading circuit with a shifting stage and corresponding reading method
US10127966B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 23, 2016 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jan 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04F10/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.