Memory device command receiving and decoding methods
US10127969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.