Gate-all-around field effect transistor having multiple threshold voltages
US10128347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jan 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.