Pattern treatment methods
US10133179B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 29, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/38
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A pattern treatment method, comprising: (a) providing a semiconductor substrate comprising a patterned feature on a surface thereof; (b) applying a pattern treatment composition to the patterned feature, wherein the pattern treatment composition comprises: a block copolymer and an organic solvent, wherein the block copolymer comprises: (i) a first block comprising a first unit formed from 4-vinyl-pyridine, and (ii) a second block comprising a first unit formed from a vinyl aromatic monomer; and (c) removing residual pattern shrink composition from the substrate, leaving a coating of the block copolymer over the surface of the patterned feature, thereby providing a reduced pattern spacing as compared with a pattern spacing of the patterned feature prior to coating the pattern treatment composition. The methods find particular applicability in the manufacture of semiconductor devices for providing high resolution patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.