Recessed solid state apparatuses
US10134596B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.