Warpage compensation metal for wafer level packaging technology
US10134689B1 · kind B1 · utility
3Cited by
0References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Sep 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.