Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same
US10134711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Mar 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the stacked semiconductor sub-assembly is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the sub-assembly and the wiring board for interconnecting devices assembled in the sub-assembly to terminal pads provided in the wiring board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.