Semiconductor memory device
US10134744B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.