High electron mobility transistor and fabrication method thereof
US10134854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Jan 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.