Transistor with asymmetric spacers
US10134859B1 · kind B1 · utility
12Cited by
9References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Nov 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.