Free layer sidewall oxidation and spacer assisted magnetic tunnel junction (MTJ) etch for high performance magnetoresistive random access memory (MRAM) devices
US10134981B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetic tunnel junction (MTJ) that avoids electrical shorts and has improved data retention is disclosed. An uppermost capping layer has a first sidewall that is coplanar with an interface between outer oxidized portions and a center ferromagnetic portion of a free layer (FL) that has a FL width (FLW). A dielectric spacer is formed on the first sidewall and oxidized outer FL portions. The pinned layer (PL) has a width (PLW) substantially greater than FLW, and a second sidewall thereon is formed by a self-aligned etch using the dielectric spacer and capping layer as an etch mask. A sidewall layer may be formed on the second sidewall and dielectric spacer but does not degrade MTJ properties since the sidewall layer does not contact the FL and PL center portions responsible for device performance. PL width>FLW ensures greater capability for data retention especially for FLW<60 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.