Link consistency in a hierarchical TLB with concurrent table walks

US10140217B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Uwe Brandt · Eppelheim, DE
• Frank Lehnert · Weil im Schönbuch, DE
• Thomas Koehler · Holzgerlingen, DE
• Markus Helms · Eppelheim, DE
• Martin Recktenwald · Eppelheim, DE

Key dates

• Filing date: Dec 17, 2017
• Grant date: Nov 27, 2018
• Expiry date: Dec 17, 2037

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.