Methods and apparatus for pattern matching using redundant memory elements
US10141055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.