Semiconductor packages
US10141252B2 · kind B2 · utility
3Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole being further defined by a first sidewall and a second sidewall of the passivation layer; a first conductive layer on the first surface of the passivation layer and the first sidewall; a second conductive layer on the second surface of the passivation layer and the second sidewall; and a third conductive layer between the first conductive layer and the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.