Semiconductor package and manufacturing method thereof
US10144634B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | Nov 7, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Nov 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.